Unable to flash bin file to EFM03 board

    • Unable to flash bin file to EFM03 board

      Hello,

      I have just began working with the EFM03 board and I just wanted to flash the default binary file that is available with the UDK Board Manager. (Attached is the about screen of the UDK Board Manager version I am using.)
      However even if the process is finished with success according to the Board Manager, after a restart cycle no image is loaded from flash.
      When I program the FPGA directly, everything works fine and I can see that the image is loaded succesfully to the FPGA.

      My setup is:
      1) EFM03
      2) EFM02 Breakout Board with pins set to take the power from an out source.

      From the power supply when the FPGA is not loaded properly, a voltage of 5V is applied with a current of 0.328 A. and only one LED on EFM03 board is lit.
      When it is properly loaded, a current of 0.92 is applied and two leds on EFM03 board are lit

      As you can guess after a flash load I still observe the lower current and one led.

      I also ensure that J18 jumper is not applied so that with a SW1 reset it shall first try to read from flash.

      Looking forward to hearing from you

      Yours Özgün
      Dateien

    • Hello Özgün,

      you can flash the default binary file to the EFM-03 flash memory, but the Artix-7 FPGA
      will not configure from it. This is - unfortunately - normal. Why?

      Vivado bitstreams, both .bit and .bin files, have compiled into them the information
      from which device they are supposed to be loaded. Our published .bin file is configured
      to be loaded via FX3 to Artix-7 connection. But a .bin file supposed to be loaded from
      the EFM-03 flash must be configured to be loaded via SPI flash, and this requires a
      different set of Vivado settings.

      I have described how to boot the EFM-03 from flash in the following support forum article:

      Programming EFM-03

      Please try this approach.

      Best regards,

      Manfred Radimersky
      Software Development
      CESYS GmbH

    • Hello Manfred,

      As requested, I have tried the process descibed in the above article and at first was not able to produce a binary file due to an error in Generate Bitstream step.
      The error message I observed is "[Designutils 20-1856] The CONFIG_MODE property value "S_SELECTMAP32" is not valid when BITSTREAM.CONFIG.SPI_BUSWIDTH is set to "4"."
      To succeed in the process, I have to untick the configuration setting that is for Slave Select Map 32 in Configuration Modes in additional Bitstream Settings and then reimplement design and rerun Generate Bitstream.
      This time I observed the same error with another message [Designutils 20-1856] The CONFIG_MODE property value "B_SCAN" is not valid when BITSTREAM.CONFIG.SPI_BUSWIDTH is set to "4".
      I have tried to untick this property as well but Vivado has warned me that this is not an selectable mode and has to be selected for all designs. I just rerun the Generate Bitstream again and somehow it worked.
      After all these additional steps I have succedded in creating a binary file.
      I have tried to rerun Generate Bitstream with the above mode selected but still get the same error.

      My Vivado version is 2017.4 and when I search for the given error message there is really not much about it over the internet.
      However the loaded binary file (loaded by both the UDK tool and through JTAG with Vivado) can not be recognised from the performance monitor and I was not able to connect to the board.
      In addition the current from the source is lower than we observed when we load the provıded binary file via FX3.

      Best Regards,

      Özgün

    • Hello Özgün,

      this problem is certainly fixable, as we use these Vivado settings to boot from flash
      with a very similar customer-specific FPGA board of ours and with Vivado 2017.4.
      But finding a solution takes some time, and unfortunately this problem is not
      covered by our free installation support.

      So my advice for you is to consult the EFM-03 hardware reference

      cesys.com/fileadmin/user_uploa…03-hardware-reference.pdf

      to see how the Artix-7 is connected to the flash memory and change the Vivado
      settings according to the documentation of Vivado 2017.4. I have specified some
      Vivado settings dialogs where changes are needed in the referenced other posting.
      For now, that is all I can do for you now.

      Best regards

      Manfred Radimersky
      Software Development
      CESYS GmbH