Programming EFM-03

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    • Programming EFM-03


      I wrote a simple user led program(to light up the user led) to see if it can be downloaded to EFM-03. When I used function "Program FPGA" in UDK3 board manager, the user led worked to show that it was successfully downloaded. When I removed the cable and plugged again, the user led wasn't on. I think it means the program was downloaded in the FPGA instead of the flash. I wonder if anyone can tell how to download the program into the flash?

      Many thanks!
    • Dear hjq310,

      The bitstream used to initialize the Artix-7 FPGA must be specifically generated
      for the intended initialization process and its "boot device". If you want to want
      to generate a version of the FPGA reference design bitstream that boots from flash,
      then you have to re-compile the bitstream using Vivado, but using different bitstream
      settings. What you have to do is:

      The bitstream settings in Vivado can be edited properly only after the
      corresponding implementation has been opened. The "Flow Navigator" option
      "Program and Debug" -> "Bitstream Settings" opens the "Project Settings"
      window with the "Bitstream" tab selected. The important option "Configure
      additional bitstream settings" can be requested only if the corresponding
      implementation has been opened before. Then the "Edit Device Properties"
      window opens. The following options are needed, special attention is only
      needed for the settings marked as "IMPORTANT":

      General tab:

      Enable Bitstream Compression: FALSE
      (IMPORTANT! Xilinx SDK does not work with compressed bitstreams)
      Enable Cyclic Redundancy Checking (CRC): ENABLE
      Enable debugging of Serial mode Bitstream: NO
      Disable communication to the Boundary Scan (BSCAN) block via JTAG: NO
      Enable JTAG Connection to XADC: ENABLE
      Enable Single Frame Cyclic Redundancy Checking (CRC): NO
      Enable Enhanced Linearity for XADC: OFF
      Enable XADC Power Down: DISABLE

      Configuration tab, Configuration Setup section:

      Configuration Rate (MHz): 3
      (meaningless, overriden by external configuration)
      Enable external configuration clock and set divide value: DIV-1
      (IMPORTANT: use external 90 MHz oscillator for configuration,
      using no clock devider)
      Configuration Voltage: UNSET
      Configuration Bank Voltage Selection: UNSET

      Configuration tab, SPI Configuration section:

      Enable SPI 32-bit address style: YES (IMPORTANT!)
      Bus width: 4 (IMPORTANT: use Quad SPI)
      Enable the FPGA to use a falling edge clock for SPI data capture: YES
      (IMPORTANT: 90 MHz configuration works only if this option is set!)

      The UDK3 BoardMan tool _cannot_ tell whether the bitstream you write into the
      flash has the correct Vivado settings for booting from flash or not.

      After you have generated an FPGA bitstream specifically compiled for
      booting from flash, you can use the "Flash FPGA design" option of the
      UDK3 board manager tool to write the bitstream into the EFM-03 flash.

      Best regards,

      Manfred Radimersky
      Software Development
      CESYS GmbH