Reset during data transfer with efm01_perf.vhd

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    • Reset during data transfer with efm01_perf.vhd

      Hello,
      I'll read out an internal BRAM with the USB Bulk Transfer function BulkWrite. I used the EFM01 performance test as a draft for my vhdl design.
      I've found out that the FX2 or the USB API sends a reset after 1024 values (exactly FX2 buffer size, 16bit), so the counter goes back to zero. After that the counter goes to its maximum value (16bit, 65535) and overflows. There is no further reset during the data transfer in the remaining block. For example I "uploaded" a block length of 0x40000 from FPGA to PC.
      The problem is still present in the newest UDK version 1.17. I've the same problem in my own design.
      Why is this reset sent and from who? FX2 interrupt INT0 or via the USBUniApi on pin PA0 (I didn't found a ResetFPGA()-call in the data transfer routines).
      Thanks for your help,
      With kind regards
      Michael Grimm

      PS: I've sent an email to cesys support team, too. It seems that most of the team is on holiday until end of august. That's why I decided to open a new thread in the forum.

    • Hello,

      the reset line is pulsed after programming the FPGA design automatically. No transfer does modify the state of this line. It's in any way recommended to ignore anything on data bus before reset is pulsed. So please try to change your design that it starts to work after reset, send some data from host and verify nothing is missed (by using counting data or other patterns).
      If you think the problem is related to the FPGA design example: I'm responsible for the host side and have minor knowledge on our FPGA designs. The person who can help further in the area is back next Monday, so please be patient in this case.

      best regards,
      Thomas Hoppe
      Thomas
      Software development
      Cesys GmbH

    • Dear Mr. Hoppe,

      I don't mean the reset after fpga configuration. That's okay and this is definitely not the reset I've seen. I tried to measure the reset pulse during first data transer but without success. However, I've seen the reset pulse activated by software function ResetFPGA() by Cesys monitor or fpga configuration. It has a pulse width of exactly 10ms as you implemented it. It seems to be that there is an "internal" reset in the FPGA I couldn't detect with an oscilloscope (I applied the rst signal to an external FPGA IO pin).
      Nevertheless I changed my design in a way that a reset between counter value 1023 and 1040 is ignored because it is unwanted. In all other cases the counter does a reset to zero.
      But what's the reason for this reset? It goes through all counters in my design and executes the reset instructions in the clocked process part.

      Please can you reproduce this problem by doing a data transfer (e.g. block length 0x10000) with the performance design example? I'll know if you see a counter reset after value 1024 in the transferred data stream, too.

      With kind regards
      Michael Grimm