Hello,
I'll read out an internal BRAM with the USB Bulk Transfer function BulkWrite. I used the EFM01 performance test as a draft for my vhdl design.
I've found out that the FX2 or the USB API sends a reset after 1024 values (exactly FX2 buffer size, 16bit), so the counter goes back to zero. After that the counter goes to its maximum value (16bit, 65535) and overflows. There is no further reset during the data transfer in the remaining block. For example I "uploaded" a block length of 0x40000 from FPGA to PC.
The problem is still present in the newest UDK version 1.17. I've the same problem in my own design.
Why is this reset sent and from who? FX2 interrupt INT0 or via the USBUniApi on pin PA0 (I didn't found a ResetFPGA()-call in the data transfer routines).
Thanks for your help,
With kind regards
Michael Grimm
PS: I've sent an email to cesys support team, too. It seems that most of the team is on holiday until end of august. That's why I decided to open a new thread in the forum.
I'll read out an internal BRAM with the USB Bulk Transfer function BulkWrite. I used the EFM01 performance test as a draft for my vhdl design.
I've found out that the FX2 or the USB API sends a reset after 1024 values (exactly FX2 buffer size, 16bit), so the counter goes back to zero. After that the counter goes to its maximum value (16bit, 65535) and overflows. There is no further reset during the data transfer in the remaining block. For example I "uploaded" a block length of 0x40000 from FPGA to PC.
The problem is still present in the newest UDK version 1.17. I've the same problem in my own design.
Why is this reset sent and from who? FX2 interrupt INT0 or via the USBUniApi on pin PA0 (I didn't found a ResetFPGA()-call in the data transfer routines).
Thanks for your help,
With kind regards
Michael Grimm
PS: I've sent an email to cesys support team, too. It seems that most of the team is on holiday until end of august. That's why I decided to open a new thread in the forum.