Are the FPGA design examples available in Verilog HDL?

We strictly recommend to learn some VHDL basics, if you want to use parts of our demo designs and understand the most important things. Perhaps you want to take a look at this tutorial: VHDL Tutorial
It is written in English. In Europe and especially in Germany VHDL is most widely used instead of Verilog. So Verilog versions of our demo FPGA designs are not planned. You will maybe have to change some VHDL port declarations from extended data types (multidimensional arrays, records) to simple data types (std_logic, std_logic_vector(<>)) in a mixed language design flow.

1. Source code or netlist:
   Normally designs are shipped as RTL style VHDL sources together with the FPGA boards at no additional costs. Sometimes standard components like FIFOs or UARTs are shipped as netlists or gate level VHDL sources/macros.
   
2. Copyright:
   All source code is copyrighted by CESYS GmbH / GERMANY, unless otherwise noted.
   
3. License:
   THE SOURCECODE IS NOT OPEN SOURCE AND IT IS NOT FREE! IT IS FOR USE TOGETHER WITH CESYS PRODUCTS ONLY! YOU ARE NOT ALLOWED TO MODIFY AND DISTRIBUTE OR USE IT WITH ANY OTHER HARDWARE, SOFTWARE OR ANY OTHER KIND OF ASIC OR PROGRAMMABLE LOGIC DESIGN WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT HOLDER!
   
4. Disclaimer of warranty:
   THE SOURCECODE IS DISTRIBUTED IN THE HOPE THAT IT WILL BE USEFUL, BUT THERE IS NO WARRANTY OR SUPPORT FOR THE SOURCECODE. THE COPYRIGHT HOLDER PROVIDES THE SOURCECODE "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE SOURCECODE IS WITH YOU. SHOULD THE SOURCECODE PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
   IN NO EVENT WILL THE COPYRIGHT HOLDER BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE SOURCECODE (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE SOURCECODE TO OPERATE WITH ANY OTHER SOFTWARE-PROGRAMS, HARDWARE-CIRCUITS OR ANY OTHER KIND OF ASIC OR PROGRAMMABLE LOGIC DESIGN), EVEN IF THE COPYRIGHT HOLDER HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
   
5. Custom specific design extensions:
   Our company offers FPGA design services as well as FPGA development boards. Custom specific designs or design extensions to our standard products are treated as any other FPGA design service and are not free of charge! For further details please contact our sales office at CESYS.