USB3FPGA automatic communication recovery

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    • USB3FPGA automatic communication recovery

      Hello,
      we need to implement an automatic recovery of the USB communication in our systems using the USB3FPGA boards.
      I have implemented all the procedures to deinit and Init again the ceUSBAPI class and to reload the ceusb driver, but it seems that it is required to program the FPGA.

      Please could you tell me if it ispossible to avoid to re-program the FPGA? I need to maintain its actual configuration.

      Best regards

      Claudio

    • Hello Claudio,

      the USB3FPGA board is a legacy device developed in year 2008. We still produce it because
      some customers still need it. The ceUSBAPI class is an early predecessor of the UDK3 FPGA
      software we supply today, and thus your FPGA software version is legacy software, too.

      Re-initializing the USB communication is a low-level feature involving the schematics and
      the Cypress FX2 firmware. We assume with a high level of probability that you would need
      the sources of our early FPGA software including the FX2 firmware and you would need to
      change it substantially. I suppose you would need to buy the FPGA software sources from us,
      which will not be cheap, and you would have to invest substantial time to adapt this software.
      This is hard work for experienced embedded systems developers.

      We do such adaptations for our customers as custom engineering jobs. But in this case I
      doubt that it would come to this. If you have serious interest in this extension, meaning
      the will to invest substantial money to do this, please contact sales@cesys.com. We are
      sorry to tell you that there is no easy way to achieve this.

      Best regards

      Manfred Radimersky
      Software Development
      Cesys GmbH

    • Hello Manfred,
      we are one of the customers (probably the only one) still acquiring your USB3FPGA.

      In the past we bought from Cesys the source files of the driver, so we are able to modify it accordingly with our needs.

      I have verified your USB6FPGA board but the communication system implemented in that board was not compatible with the USB3FPGA one.

      Since we did not bougth the FX2 firmware source code, what I need to know is if it is mandatory reprogramming the FPGA after the download of the FX2 firmware or if there is a way to say to the FX2 controller to restart the communication.

      What I have verified is that, after a crash of the USB connection, the only way we have to recover the communication is to reprogramming the FPGA even if the driver has been correctly reloaded and reinitialized. But this should not be necessary if the crash happened at the pc level (for example due to a USB port unconnection).

      Please, let me know

      Best regards
      Claudio Bertacchini
      R&D Manager
      IGEA SpA - Italy

    • Hello Claudio,

      long time not seen! I hope you are well.

      I'm afraid a disorderly break of the communication between FPGA and FX-2 leads to the fact that the statemachine in the FPGA and the slave-FIFO configuration must be set up again. They are then no longer synchronous. Even if it should be possible to do a USB reset without FPGA reconfiguration (if this is possible Thomas Hoppe is looking at it and will come with his estimation) the FPGA-FX2 communication would be stuck.
      The best method would be to make the USB connection more reliable by using short and good cables.
      If it is important that data survives a reset, it would have to be stored in the SRAM and the FPGA would have to check the status of the SRAM after the restart.


      Best regards
      Manfred Kraus

    • Hello Manfred,
      nice to ear from you again. I'm fine, thanks. I hope you too.

      I was hoping that doing a reset of the pipes could solve the problem, but it seems useless.

      Your suggestion, to save the state in RAM, is good so I try to implement it. But if Thomas can identify a workaround to recover the synchronization between the FX2 and the FPGA usign the driver and the API I can implement it.
      In any case Idon't want to change the FX2 firmware.

      Best regards
      Claudio

    • Hello,
      yesterday I did some tests on the fpga,using the chipscope, to understand what was really happening.
      I discovered that the FX2 controller during the connection with a usb port of the PC always sends a signal on the progb line causing the clearing of the fpga. This happens only with Linux systems because the negotiation with the pc is done in a different way under Windows.

      I have also verified that is not possible to store the status of the fpga into the ram to try to recover it. The ram is completely used by the application.

      From my point of view there are the following ways to try to avoid the erasure of the fpga:
      1) modify the FX2 firmware avoiding to send the pulse on the progb line during the connection with a usb port of a pc. But I would like to avoid this unless strictly necessary.
      2) remove the resistor R9 and doing a connection with a signal allowing the FPGA programming only after a power off (line FX2_RESET# ?)

      Do you have any other suggestion about how to solve this issue?

      PS:
      During my tests the board I was using suddenly changed its manufacturing codes. Now it is seen as 04b4:8613 (a FX2 USB 2.0 development kit). Is it possible to recover the correct cesys board identification?

      Thanks
      Claudio