Hi,
I want to activate UART interface through mini USB connector on the EFM03 board. For that, I added microblaze processor and AXI Uartlite block in EFM03_exdes example project. I added following lines in the constraint file to connect UART pins.
set_property PACKAGE_PIN T7 [get_ports {uart_rtl_rxd}]
set_property IOSTANDARD LVCMOS33 [get_ports {uart_rtl_rxd}]
set_property PACKAGE_PIN R6 [get_ports {uart_rtl_txd}]
set_property IOSTANDARD LVCMOS33 [get_ports {uart_rtl_txd}]
Although synthesis passed without a problem, during implementation phase I received following error.
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs:
DDR3_ck_p[0] (DIFF_SSTL135, requiring VCCO=1.350) and uart_rtl_rxd (LVCMOS33, requiring VCCO=3.300)
It seems the UART pins are also in the same bank with DDR3 memory pins. What should I add in the constraint file to set UART interface?
Regards,
Burak Kelleci
I want to activate UART interface through mini USB connector on the EFM03 board. For that, I added microblaze processor and AXI Uartlite block in EFM03_exdes example project. I added following lines in the constraint file to connect UART pins.
set_property PACKAGE_PIN T7 [get_ports {uart_rtl_rxd}]
set_property IOSTANDARD LVCMOS33 [get_ports {uart_rtl_rxd}]
set_property PACKAGE_PIN R6 [get_ports {uart_rtl_txd}]
set_property IOSTANDARD LVCMOS33 [get_ports {uart_rtl_txd}]
Although synthesis passed without a problem, during implementation phase I received following error.
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs:
DDR3_ck_p[0] (DIFF_SSTL135, requiring VCCO=1.350) and uart_rtl_rxd (LVCMOS33, requiring VCCO=3.300)
It seems the UART pins are also in the same bank with DDR3 memory pins. What should I add in the constraint file to set UART interface?
Regards,
Burak Kelleci