EFM03 Reference Design and Vivado 2017_2

    • EFM03 Reference Design and Vivado 2017_2

      Hi,

      I tried to synthesize the EFM03 reference design (version 1.2.1, loaded today from support page) with Vivado version 2017_2.
      During synthesis I got errors in file axi_bram_ctrl_v4_0_rfs.vhd. I was able to fix them. But afterwards I get an error in
      file fx3_axis_dma_interface.vhd, which is encrypted. No chance for me to fix the error.

      Question to Cesys team: Are you sure, that the EFM03 reference design is really working with Vivado 2017_2 ?

      I did a fresh installation of Vivado WebPack Edition. According the comments on download page the version 2017_2 was used
      for that design.

      With kind regards,

      Torsten Kramer

    • Hello Mr Kramer,

      as a first test, I have used Vivado 2017.4. Here is what I have done:

      1. unpacked our efm03_reference_design-v1.2.1.zip
      2. opened the included xpr file with Vivado 2017.4
      3. auto-upgraded the used Xilinx modules to 2017.4
      4. run synthesis
      5. run implementation

      The synthesis and implementation was successful in this try. I'll
      check a bit more soon.

      Best regards

      Manfred Radimersky
      Software Development
      CESYS GmbH

    • Hello Mr. Radimersky,

      I can confirm, that it's possible to synthesize and implement the example design with Vivado 2017.4.

      Please add a corresponding comment to reference design download page, the Vivado 2017.2 is obviously not
      the right version for that design.

      Thanks for the fast support !

      Regards,

      Torsten Kramer

    • Hello Mr Kramer,

      I have tested both Vivado 2017.4 and 2020.1 with our EFM-03 reference design,
      and it works with both of these Vivado versions. Only the "Gernerate Bitstream"
      yields two errors because Vivado has changed the parsing of some files from case
      insensitve to case sensitive:

      [DRC NSTD-1] Unspecified I/O Standard: 192 out of 319 logical ports use I/O standard
      (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may
      cause I/O contention or incompatibility with the board power or connectivity
      affecting performance, signal integrity or in extreme cases cause damage to the
      device or the components to which it is connected. To correct this violation,
      specify all I/O standards. This design will fail to generate a bitstream unless all
      logical ports have a user specified I/O standard value defined. To allow bitstream
      creation with unspecified I/O standard values (not recommended), use this command:
      set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the
      Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a
      .tcl file and add that file as a pre-hook for write_bitstream step for the
      implementation run. Problem ports: GPIO_5_tri_io[31:0], GPIO_4_tri_io[31:0],
      GPIO_3_tri_io[31:0], GPIO_2_tri_io[31:0], GPIO_0_tri_io[31:0], and GPIO_1_tri_io[31:0].

      [DRC UCIO-1] Unconstrained Logical Port: 192 out of 319 logical ports have no user
      assigned specific location constraint (LOC). This may cause I/O contention or
      incompatibility with the board power or connectivity affecting performance, signal
      integrity or in extreme cases cause damage to the device or the components to which
      it is connected. To correct this violation, specify all pin locations. This design
      will fail to generate a bitstream unless all logical ports have a user specified
      site LOC constraint defined. To allow bitstream creation with unspecified pin
      locations (not recommended), use this command: set_property SEVERITY {Warning}
      [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g.
      launch_runs Tcl command), add this command to a .tcl file and add that file as a
      pre-hook for write_bitstream step for the implementation run. Problem ports:
      GPIO_5_tri_io[31:0], GPIO_4_tri_io[31:0], GPIO_3_tri_io[31:0], GPIO_2_tri_io[31:0],
      GPIO_0_tri_io[31:0], and GPIO_1_tri_io[31:0].

      These two errors can be fixed by replacing the strings "gpio_" with "GPIO_" in
      file efm03_constr.xdc, or by replacing the file efm03_constr.xdc from our
      reference design with the file extracted from the attached zip file. With this
      fixed file the following steps should work with Vivado 2017.4 and 2020.1:

      1. unpack our efm03_reference_design-v1.2.1.zip
      2. replace the file efm03_constr.xdc with the version in the attached zip file
      3. open the included xpr file with Vivado 2017.4 or 2020.1
      4. auto-upgrade the used Xilinx modules to 2017.4 or 2020.1
      5. run synthesis
      6. run implementation
      7. generate bitstream

      Best regards

      Manfred Radimersky
      Software Development
      CESYS GmbH
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