Hi,

For the last two months we have been trying to develop on EFM03 Board based on your reference design.
At first we were using Vivado Blocks, so we do not really utilize debugging functionality with the EFM03 board.
However, when we developed in house blocks and then integrated them to the reference design, we need to debug some parts of our design.
In our quest so far for debugging, we were not able to connect to the debugger with our XILINX Platform Cable USB 2, and always get the warning below.

The Warning is:
INFO: [Labtools 27-1434] Device xc7a200t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3403] Dropping logic core with cellname:'ila_deneme' from probes file, since it cannot be found on the programmed device.

For your knowledge we are working with Vivado 2017.4, which has the automatic debug option(where you just left click on any connection and choose debug).
In all my designs I checked the synthesized output for debug cores, and I can see the signals, and cores available in my design.

Below is a list of what I've tried so far to get over this problem:
1) Instead of automatically adding ILA, add one by hand and make the debug connections per hand
2) Route out the debug signals as ports and connect it to an external ILA to debug.
3) Set up a Debug core from synthesized design
4) All of the solutions reccomended in xilinx.com/support/answers/64764.html

In addition when we tried to debug with basic designs, not based on your reference design with the same connectors and cables, we were succesful to debug with the board.
The designs were basic counters connected to a 10MHz. clock we phase lock looped from 200 Mhz. differential clock.

It is urgent that we need assistance in this and it will be great if you can share with us a reference design that you can debug inhouse with Vivado 2017.4 or help us with a version of Vivado we shall use to debug your design.

Thanks
Özgün

Hello Manfred,

Maybe I was not clear on my question. We are designing our own blocks basing it on your reference design, and we want to debug our own signals. We do not aim to debug any part of the reference design.
However, each time we connect the ILA to one of our own signals it gives the above error, which is a result of your reference design(since the clock for the ILA is also provided from the MIG DDR Controller ui_clk pin), and therefore we are expecting you to at least provide us with a reference design that provides a clean clock signal we can use for debugging.

Hope this clarifies everything.

Looking forward to hearing from you

Özgün