Hi all,
In my application I need to transfer data from the PC to the SRAM in the USB3FPGA card and viceversa. I did this for a long time using a code sent to me on 2008 from cesys. Now after the last changes in the fpga design, this part of the design stopped to work and I cannot have a correct access to the SRAM.
I also found that the old code works properly only using the Xilinx ISE
10.1. If I use the last version of ISE that code is no longer working
due to timing issues.
I read the documentation, but the information about the bulk access timing are not complete and it is impossible to me understand how to fix the bug.
I think that part of the issue could be due to the usage of the BUFGDLL as a clock buffer because it is no longer supported and .
Attached you find the two files used to manage the bulk transfer and the SRAM access.
Please, could you give me some suggestions about how to fix the problem?
Thank you
Claudio Bertacchini
In my application I need to transfer data from the PC to the SRAM in the USB3FPGA card and viceversa. I did this for a long time using a code sent to me on 2008 from cesys. Now after the last changes in the fpga design, this part of the design stopped to work and I cannot have a correct access to the SRAM.
I also found that the old code works properly only using the Xilinx ISE
10.1. If I use the last version of ISE that code is no longer working
due to timing issues.
I read the documentation, but the information about the bulk access timing are not complete and it is impossible to me understand how to fix the bug.
I think that part of the issue could be due to the usage of the BUFGDLL as a clock buffer because it is no longer supported and .
Attached you find the two files used to manage the bulk transfer and the SRAM access.
Please, could you give me some suggestions about how to fix the problem?
Thank you
Claudio Bertacchini