moving from USB3FPGA to USBS6

    Diese Seite verwendet Cookies. Durch die Nutzung unserer Seite erklären Sie sich damit einverstanden, dass wir Cookies setzen. Weitere Informationen

    • moving from USB3FPGA to USBS6

      Hi all,
      I'm trying to move my FPGA design from the USB3FPGA board to the USBS6.
      Since my design requires to have a direct access to the external RAM and to the internal dual-port RAM to read/write data, I suppose it has to act as a master to do that.
      So I need some help to learn how to use my design as master and to interface it with the SDRAM.
      I have instantiated my design as a master block into the wishbone architecture

      Thank you
      Regards
      Claudio Bertacchini

    • Dear Mr. Bertacchini,

      I don´t know, if I have understand you right.

      You know how to access to RAM but you want to write a Wishbone-Master, isn´t it?

      It is very simple.
      If you want, I send you a small example-code.

      1. Change NR_OF_MASTERS to 2 (wishbonde_pk.vhd)
      2. Connect the Master to the second Master-Port (MA_MY_MASTER_ID)

      inst_wb_ma_my_master_pkg : wb_ma_my_master
      generic map (
      NR_OF_DBGPORTS => 1
      )
      port map (
      syscon_i => syscon,
      master_o => intercon.masters.master(MA_MY_MASTER_ID),
      slave_i => intercon.masters.slave(MA_MY_MASTER_ID),

      DECODER_I => pin_hex_n_i,

      debug => open
      );

      3. In the master-design:
      master.sel <= (others => '1');
      master.cyc <= master.stb;
      master.stb <= '1';

      master.adr <= x
      master.dat <= X
      master.we <= '1'; or '0'

      wait until slave.ack ='1'
      if slave.ack = '1' then
      master.stb <= '0';
      end if;

      4. If you want to read data from the wishbone-slave, do this now.

      that´s it.
      Torsten
      FPGA/LABView development
      Cesys GmbH

    • moving from USB3FPGA to USB6

      Dear Torsten,
      thank you for your reply.
      I think you have correctly understood my problem: my old design was having access to the SRAM and to several registers, now I need to integrate it with the whisbone architecture.
      About the memory, I'm not absolutely sure to know correctly how to access to the external RAM. I was used to access the SRAM on the USB3FPGA, but in the USB6 perhaps I have also to drive the CAS and RAS signals. Am I correct or the whisbone DRAM interface module manages those signals automatically letting me to drive only the standard signals (WE, CS, OE)? I also need to write data into the DRAM with a single clock access at 20MHz. Is it possible or do I have to create a pipeline?

      I appreciate to receive the simple example you could send me. Please send it to this email address: c.bertacchini@igeamedical.it

      I also did the point 1 but instead of the point 2 I added a component referring to my master in the usb_soc_top.vhd file. Is it the same?
      If not, I guess I have to create a .pkg file with the code you wrote in your post adding it to the project library. Is it correct?
      Where I have to set the variable MA_MY_MASTER_ID?

      Thanks again
      Regards

      Claudio Bertacchini