Hi all,
I'm trying to move my FPGA design from the USB3FPGA board to the USBS6.
Since my design requires to have a direct access to the external RAM and to the internal dual-port RAM to read/write data, I suppose it has to act as a master to do that.
So I need some help to learn how to use my design as master and to interface it with the SDRAM.
I have instantiated my design as a master block into the wishbone architecture
Thank you
Regards
Claudio Bertacchini
I'm trying to move my FPGA design from the USB3FPGA board to the USBS6.
Since my design requires to have a direct access to the external RAM and to the internal dual-port RAM to read/write data, I suppose it has to act as a master to do that.
So I need some help to learn how to use my design as master and to interface it with the SDRAM.
I have instantiated my design as a master block into the wishbone architecture
Thank you
Regards
Claudio Bertacchini