XV2DDR

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    • XV2DDR SPEC03 false pin description



      Dear Cesys Team,
      unfortunately there is a mistake in the product specification for the XV2DDR_EVAL Evaluation Board (SPEC03 (v1.0) Oktober, 25, 2002).

      On Page 4 Table J8 the Virtex Pin H3 is assigned to Pin5 AND Pin8 of the J8 connector (see attached picture). Obviously, this can't be correct.
      Do you have an errata for this specification?
      If not, could you please check and send me the proper pin assignments?

      Thanks.



      I compared J8 pin 5 and pin 8 description against the schematics of the XV2DDR and its EVAL-board.
      You are right. The description in SPEC03 V1.0 was not correct. It is corrected in V1.1 now.
      Thank you very much for reporting this error.

      Manfred Kraus
      Cesys GmbH