Hello world,
I have inherited an unfinished application where the USB3FPGA may be a good fit, subject to positive answers to a couple of questions, but I am new to FPGAs and VHDL so am looking to increase confidence before suggesting USB3FPGA to Management. This had been a "start from scratch" project but due to resource changes we are now looking at our options to buy rather than build in order to save time and decrease risk.
The application isn't trivial but seems quite simple in FPGA terms, conceptually similar to a slightly cut down version of the Spartan-based logic analyzer at sump.org [1] which I discovered very recently (long after this project began). One difference is that the data to be recorded in any given location is based on the already recorded data from earlier in the run, ie each cycle to be recorded needs a read modify write (an increment) rather than just a write. Another difference is that there is some preprocessing to ignore certain incoming cycles. The external clock will be an external clock at around 40MHz. If you were to imagine this as a "memory access profiling" machine (to help identifying hotspots) you would be surprisingly close.
So, the two questions:
Q1: The USB3FPGA uses Cypress 7106 SRAM @ 10ns which (as a mostly-software person) I think should be up to the job of RMW @ 40MHz and indeed was the RAM picked earlier when we were intending this as a start-from-scratch project. Am I safe to assume RMW @ 40MHz? Is this easy to do? I've used the Xilinx tools and a DCM to get a four phase clock derived from our external one but haven't yet found a way to tell ISE how to drive the bus phases needed for the read then the write during one incoming clock cycle. The sump.org analyser uses a very different SRAM with separate ports for input and for output so offers nothing to be inspired by, and I haven't yet found any relevant Xilinx or similar app notes or code snippets.
Q2: Many SRAM connections seem to come out to the expansion connector, but are shared with other IO. We would want to add extra SRAMs on a daughtercard (maybe 3 extra, ideally up to 7) and still be able to have 30 or so state inputs to the analyser. Again, at first glance this would seem to be possible, but have I understood correctly that all the necessary SRAM connections are available and we'd still have around 30 inputs for recording?
Many thanks in advance,
Vielen Dank,
JohnW
[1] sump.org/projects/analyzer/
I have inherited an unfinished application where the USB3FPGA may be a good fit, subject to positive answers to a couple of questions, but I am new to FPGAs and VHDL so am looking to increase confidence before suggesting USB3FPGA to Management. This had been a "start from scratch" project but due to resource changes we are now looking at our options to buy rather than build in order to save time and decrease risk.
The application isn't trivial but seems quite simple in FPGA terms, conceptually similar to a slightly cut down version of the Spartan-based logic analyzer at sump.org [1] which I discovered very recently (long after this project began). One difference is that the data to be recorded in any given location is based on the already recorded data from earlier in the run, ie each cycle to be recorded needs a read modify write (an increment) rather than just a write. Another difference is that there is some preprocessing to ignore certain incoming cycles. The external clock will be an external clock at around 40MHz. If you were to imagine this as a "memory access profiling" machine (to help identifying hotspots) you would be surprisingly close.
So, the two questions:
Q1: The USB3FPGA uses Cypress 7106 SRAM @ 10ns which (as a mostly-software person) I think should be up to the job of RMW @ 40MHz and indeed was the RAM picked earlier when we were intending this as a start-from-scratch project. Am I safe to assume RMW @ 40MHz? Is this easy to do? I've used the Xilinx tools and a DCM to get a four phase clock derived from our external one but haven't yet found a way to tell ISE how to drive the bus phases needed for the read then the write during one incoming clock cycle. The sump.org analyser uses a very different SRAM with separate ports for input and for output so offers nothing to be inspired by, and I haven't yet found any relevant Xilinx or similar app notes or code snippets.
Q2: Many SRAM connections seem to come out to the expansion connector, but are shared with other IO. We would want to add extra SRAMs on a daughtercard (maybe 3 extra, ideally up to 7) and still be able to have 30 or so state inputs to the analyser. Again, at first glance this would seem to be possible, but have I understood correctly that all the necessary SRAM connections are available and we'd still have around 30 inputs for recording?
Many thanks in advance,
Vielen Dank,
JohnW
[1] sump.org/projects/analyzer/