EFM03 UART Access

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    • EFM03 UART Access


      I want to activate UART interface through mini USB connector on the EFM03 board. For that, I added microblaze processor and AXI Uartlite block in EFM03_exdes example project. I added following lines in the constraint file to connect UART pins.

      set_property PACKAGE_PIN T7 [get_ports {uart_rtl_rxd}]
      set_property IOSTANDARD LVCMOS33 [get_ports {uart_rtl_rxd}]
      set_property PACKAGE_PIN R6 [get_ports {uart_rtl_txd}]
      set_property IOSTANDARD LVCMOS33 [get_ports {uart_rtl_txd}]

      Although synthesis passed without a problem, during implementation phase I received following error.
      [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs:
      DDR3_ck_p[0] (DIFF_SSTL135, requiring VCCO=1.350) and uart_rtl_rxd (LVCMOS33, requiring VCCO=3.300)

      It seems the UART pins are also in the same bank with DDR3 memory pins. What should I add in the constraint file to set UART interface?


      Burak Kelleci
    • Dear Mr Kelleci,

      thank you for your question about FPGA balls T7 and R6! These FPGA balls have a brief
      description in our document UG-120, "EFM-03 hardware reference", on page 13. These
      FPGA balls use a bank voltage of 1.35V, but they are connected to the FTDI Chip FT230X
      using a 1.35V to 3.3V level shifter on-board. You must not change the voltage in the
      FPGA design, the board schematic changes the voltage for you.

      Your question suggests it would be nice if our EFM-03 reference design already included
      a complete Xilinx UART Lite block with all necessary connections to the debug UART
      FPGA balls. We will consider such an extension for future releases of the reference design.

      Best regards

      Manfred Radimersky
      Software Development
      Cesys GmbH