Clock to custom VDHDL module - Wishbone - PCIS3 board

    • Clock to custom VDHDL module - Wishbone - PCIS3 board

      Hello All,

      I have a custom VHDL module which has an asynchronous input called start. When it is active the VHDL module (its a state machine) starts its operation. I have intantiated VHDL module in wb_sl_gpio (making it a gpio slave) file of your wishbone bus system (which comes with PCIS3 baord). I am activating the start button using your software (I have modified the code to assign an address for my register and write to it, its working properly, I checked with your software). But I could not get the correct reult. I tried to send the clock in many ways like from intercon.syscon.clk, declared IBUFG in top module and sent the clock to syscon module and my custom VHDL module, instantiated 2 more DCMs for deskewing etc. But some how my the design is entering into metastability. Can you please tell me which is the best way to avoid this and provide synchronous clocks? Can I avoid creating two clock domains?

      Can you please suggest me a solution?

      Thanks in advance. By the way, thanks to cesys. We bought few more boards.

      Best Regards,

      Ranga Prasad.

    • Clocks in CESYS PCIS3BASE Demo FPGA Design

      Hello,

      there is always the risk of metastability in an asynchronous system design. Our example FPGA design for PCIS3BASE uses a single clock domain, i. e. "wishbone.syscon.clk"-signal in "wb_sl_gpio"-module. Maybe this clock signal is named differently in other modules ("intercon.syscon.clk", ...), but after synthesis there is only one physical clock domain.
      Synchronizing asynchronous control signals to system clock domain is often an appropriate design strategy to avoid several clock domains. This can be done by routing the asynchronous signals through two consecutive flip-flops clocked by target clock domain.

      Best regards
      CESYS development engineer / FPGA design