EFM03 AXI-FX3 GPIO register Address

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    • EFM03 AXI-FX3 GPIO register Address

      Hello!
      I'm pretty new to this, so please forgive any obvious questions.
      Considering the Address Range of the AXI-FX3 interconnect:
      The following map is from the Datasheet (p.19):



      NameInterfStart Addr.RangeEnd Addr.
      GPIO 0axi_gpio_0S_AXI0x8000_000064KB0x8000_FFFF
      GPIO 1axi_gpio_1S_AXI0x8000_100064KB0x8001_FFFF
      GPIO 2axi_gpio_2S_AXI0x8000_200064KB0x8002_FFFF
      GPIO 3axi_gpio_3S_AXI0x8000_300064KB0x8003_FFFF
      GPIO 4axi_gpio_4S_AXI0x8000_400064KB0x8004_FFFF
      GPIO 5axi_gpio_5S_AXI0x8000_500064KB0x8005_FFFF





      My EFM03 has a little test programm based on the Reference Design which is toggling some GPIOs. All the Data of the GPIO_0 is between 0x8000.0000 and 0x8000.001F

      My question is why is there 64kbit of space for a 32bit variable ? What are the other values for ?

      Furthermore, the void readBlock(...) function only works with increments of 4 considering the address. I get the absolute same results for reading 0x8000.0000, 0x8000.0001,0x8000.0002 and 0x8000.0003. Is this correct ?


      Cheers, Simon
    • Hello Simon,

      I assume you mean our user guide "UG121 - AXI-FX3-Interface v1.2" by
      datasheet. Our EFM-03 reference design is based on the AXI bus. The
      address ranges of the page 19 table mean AXI bus ranges of AXI slaves,
      and these addresses are byte based.

      The AXI slaves called axi_gpio_? are instantiations of the Xilinx LogiCORE
      IP AXI GPIO v2.0 described in Xilinx product guide PG144. You can use
      Xilinx DocNav to view the Xilinx data sheets and product guides.

      Accessing addresses in the Range between 0x8000000 and 0x8000001F
      writes to or reads from the register set of the GPIO module, to be precise.
      One GPIO register set can fit into 256 bytes and does not require 64 KBytes
      (not 64 kbit as you wrote). The AXI interconnect allows only powers of 2 as
      address range sizes. We chose 64 KByte ranges because of simplicity only.

      Accessing addresses that are not mapped to specific registers has
      undefined results.

      The function readBlock() should be used with 4-byte-aligned base addresses
      only (integer multiples of 4), and with sizes that are multiples of 4 only, too.

      Helping with details of our FPGA reference designs, using Vivado and
      with Xilinx IP blocks is not included in our free installation support.
      Usually we help in these fields in our paid support or projects only.

      Best regards

      Manfred Radimersky
      Software Development
      CESYS GmbH