Interface of a custom VHDL module to the CESYS's USB modules for EMF01

    • Interface of a custom VHDL module to the CESYS's USB modules for EMF01

      We have designed a VHDL module that reads from the General Purpose IOs of the EMF01 board, 16bit wide data at bursts of 10MHz rate. These bursts occur at a rate of 2KHz. We want now to transmit this data via USB to the PC using the CESYS's USB VHDL module. How does someone interfaces the 16bit wide output of our module to the CESYS's VHDL module?

      Thanks
      Theodoros Athanasopoulos

    • Data Width in CESYS FPGA Demo Designs

      Hello,

      we use a 32 bit data bus width in our example WISHBONE FPGA designs. A data width conversion has to be done in your user application FPGA design, if you want to use our USB/WISHBONE example module" wb_ma_fx2.vhd". Conversion can be done i. e. by using manually implemented register buffering schemes or by using FIFO buffers with mismatched port width.

      Maybe Xilinx application note XAPP261 - Data-Width Conversion FIFOs Using the Virtex-II Block RAM Memory (sources xapp261.zip) could be interesting for you.

      Best regards
      CESYS development engineer / FPGA design

    • Using Slave FIFO Mode directly

      Hello,

      of course it is possible to use low level slave FIFO controller "fx2_slfifo_ctrl.vhd" together with software API functions ReadBulk() and WriteBulk(). Your user application has to ensure 512 bytes USB bulk packet alignment, if you want to use it. The 512 byte alignment is normally easy to meet in data streaming applications with endless data transfers.

      Best regards
      CESYS development engineer / FPGA design

    • Hello,

      EFM01 is designed to be connected to a carrier-board with corresponding connectors or by soldering EFM01 to the board. Using ribbon cables is not the recommended way to do it. If there is no other way, then reduce the cable length to the absolut minimum possible to not add more inductance to the signal lines as necessary and use as much ground lines as you can afford. To minimze ground bounce use the slowest slew-rate compatible with your design and reduce simultaneous switching I/O. Spreading I/O may also be a good idea.



      Best regards,
      Michael Hufnagel
      [Dipl.-Ing. (Univ.) Elektrotechnik]

      CESYS Gesellschaft für angewandte Mikroelektronik mbH
      Hardware- Entwicklung und Validierung

    • Drivers of EFM-01 and UDK

      We have bought a small number of EMF-01's sometime ago. Now we had to upgrade our computers to windows 7 64 bit and we are facing problems with EFM-01 drivers and API's. Is your new UDK the solution to our problem? Are we liable for a license of the new UDK?

      Looking forward to your reply
      Theodoros Athanasopoulos