Suchergebnisse

Suchergebnisse 1-6 von insgesamt 6.

  • Hallo kuba, AI-8 bis AI-13 befinden sich auf dem dem 25-poligen Stecker. Die Anschlussbelegung steht auf Seite 9 des Handbuchs. Handbuch: cesys.com/fileadmin/user_uploa…ts/CEBO/ug105-cebo-lc.pdf

  • Ich habe eben ein CEBO-LC zusammen mit dem "CEBO-LC Data-Logger" in Betrieb genommen. Wenn ich Mode auf "TRG Input" stelle wird jedes mal wenn ich den Eingang "TRG" mit 5 Volt verbinde ein Trigger ausgelöst. In der unteren Statuszeile ist ein grüner Punkt und der Text "... Running". Wenn ich dasselbe ohne CEBO-LC oder ohne Treiber mache, ist ein der Statuszeile ein roter Punkt mit dem Text "DEMO-MODE" und beim Mode "TRG Input" werden mit voller Geschwindigkeit immerzu Daten aufgenommen. Das lieg…

  • Today I've got a question from a customer. He wrote: Zitat: „Hello Manfred, I am considering buying Vivado. Do you think I need System Edition version, or Design Edition is enough? “ This is a question that goes deeper than it seems at first glance. You need the system edition when you want to use HLS and/or System Generator for DSP. If you need to implement DSP functionality, floating point mathematics or such, or if you want to include Mathlab in your flow, then the System Generator is helpful…

  • Yahoooooo! It took longer than expected but I like the result. The new Cesys homepage on cesys.com has a clear structure now. It is not multilingual any more because of a reason and a warranting. Keeping a multilingual website currently is not as easy as it seems - and it takes twice the time. This was the reason to have it in English language only. The defense is that someone who does not understand information presented in english language, will not be able to use FPGA development tools, compi…

  • We will introduce a new IP core for EFM-02 next week: a AXI4 busmaster bridge to FX3's GPIF2 slave FIFO interface (EZ-USB® FX3™ USB Controller - Cypress Semiconductor). It is already working nicely and stable but needs some throughput optimizations. Using this IP, the PC can access an AXI bus inside the FPGA using the "memcpy"-like read/write commands of the UDK3. In parallel to other AXI4 bus masters like Microblaze or something. This makes the usage of USB 3.0 in projects so amazing easy... In…

  • A sign of life

    Makra - - Developers blog

    Beitrag

    Hello to all! After a long time, here is a sign of life. I'm just here to bring the forum back on track. It had to be closed temporary because it was flooded by spam bots. Now, it is protected by a more secure registration process. In addition, the Cesys homepage desperately needs a relaunch. So much to do, so little time. Nevertheless, I will report from time to time what is new, what our developers are working, and what new things, we have in the pipeline. Stay tuned.