efm02_perf_top_XC6SLX45 Project Status (02/13/2014 - 12:06:15) | |||
Project File: | efm02_perf_top_XC6SLX150.xise | Parser Errors: | No Errors |
Module Name: | efm02_perf_top_XC6SLX45 | Implementation State: | Programming File Not Generated |
Target Device: | xc6slx45-3fgg484 |
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Product Version: | ISE 14.7 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | ||||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Current | Do 13. Feb 12:05:53 2014 | |
WebTalk Log File | Current | Do 13. Feb 12:06:15 2014 |