Cesys support Forum for FPGA boards and CEBO DAQ

Cesys customer support and general FPGA discussions

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  • Practical Explanation ( For Example ) :- `1st of all can you tell me every single seconds detail from that time when you born ?? ( i need every seconds detail ?? that what- what you have thought and done on every single second ) can you tell me every…
  • djhopkins2 -

    Replied to the thread IP support in newer Vivado 2023.2.

    Post
    We had an old dev board that I was trying to get working when I ran into that issue. I ended up testing that hypothesis with Vivado 2022 and it compiled with minimal issues. We have moved on to looking at ethernet for data transfer but I wanted to pass…
  • maradim -

    Replied to the thread IP support in newer Vivado 2023.2.

    Post
    Dear Mr Hopkins, thank you for reporting this issue. We have noticed this problem, too. We will have to update our Vivado IPs. A decision when to do this will take one or a few weeks. Best regards Manfred Radimersky Software Development CESYS GmbH
  • djhopkins2 -

    Posted the thread IP support in newer Vivado 2023.2.

    Thread
    Attempting to compile the BeastLink V1_0 IP block into a test design yields an error. Source Code (1 line)It appears that Xilinx is now obsoleting IP encryption keys after 5 years. The file i question is using the (key_keyname = "xilinxt_2017_05") key…